1. Field of the Invention
This invention generally relates to a semiconductor device, an electronic device and a fabrication method of the same, and in particular, relates a semiconductor device and an electronic device having a pad electrode and a fabrication method of the same.
2. Description of the Related Art
A semiconductor device using a high frequency wave such as a microwave or a milliwave is used in an electronic device such as a cellular phone or a satellite receiver. In the semiconductor device or in the electronic device, a semiconductor substrate (semiconductor chip) having an active element or a passive element is mounted on a package or on a mounting substrate in the electronic device. A pad electrode is provided on the semiconductor substrate. The pad electrode is used for electronic connection between the semiconductor chip and the package or the mounting substrate.
FIG. 1A and FIG. 1B illustrate a structure of the pad electrode of a semiconductor chip in accordance with a conventional embodiment. As shown in FIG. 1A, a first pad layer 22 is provided on a semiconductor substrate 10. A first insulating layer 32 is provided on the semiconductor substrate 10 and on a surrounding of the first pad layer 22. A second pad layer 24 is provided on the first pad layer 22. A lower pad layer 20 is composed of the first pad layer 22 and the second pad layer 24. A second insulating layer 38 is provided on the first insulating layer 32 and on a surrounding of the lower pad layer 20. An upper pad layer 40 is provided on the lower pad layer 20. A pad electrode 12 is composed of the lower pad layer 20 and the upper pad layer 40. As shown in FIG. 1B, a connecting terminal 50 is provided on the upper pad layer 40. The connecting terminal 50 is composed of a solder for connecting the pad electrode electrically to a package or a mounting substrate on which the semiconductor chip is mounted. Japanese Patent Application Publication No. 9-205096 discloses a case where the lower pad layer 20 is composed of a layer.
In the conventional embodiment, the first pad layer 22 and the second pad layer 24 of the lower pad layer 20 are used for a wiring of the semiconductor chip. And a metal having a low electrical resistance such as Au is used for the first pad layer 22 and the second pad layer 24. A bump such as a solder is used as the connecting terminal 50 in order to connect the pad electrode electrically to a package or a mounting substrate. A material acting as a barrier layer is used as the upper pad layer 40 in order to prevent the diffusion of a material of the lower pad layer 20 into the connecting terminal 50.
In a semiconductor device using a high frequency wave, it is necessary to reduce a capacity of the pad electrode 12. On the other hand, in a case where the connecting terminal 50 is provided on the pad electrode 12 as in the case of the conventional embodiment, it is necessary to maintain adherence intensity between the connecting terminal 50 and the pad electrode 12.
FIG. 2A and FIG. 2B illustrate a case where the pad electrode 12 is formed to be small in order to reduce the capacity of the pad electrode 12 in the conventional embodiment. As shown in FIG. 2A, when the pad electrode 12 is small, a width B of a recess on a top face of the upper pad layer 40 is smaller than a width A of a recess on a top face of the upper pad layer 40 shown in FIG. 1A. In particular, the recess is deep and has a small width, in a case where the lower pad layer 20 is composed of the first pad layer 22 and the second pad layer 24, and the first insulating layer 32 and the second insulating layer 38 cover the surrounding of the first pad layer 22 and the second pad layer 24, respectively. The width B is approximately 10 μm, in a case where a width and a length of the pad electrode 12 is less than 50 μm and a thickness of the upper pad layer 40 is 10 μm to 20 μm in order to obtain a barrier property and relax a stress. In this case, as shown in FIG. 2B, a void 52 is formed in the recess when the connecting terminal 50 is formed on the upper pad layer 40 with a printing method (metal mask). Such a void 52 may make a high electrical resistance between the upper pad layer 40 and the connecting terminal 50. That is, impedance is increased when a high frequency wave is input or output through the pad electrode 12 and the connecting terminal 50. And the impedance causes a high frequency wave loss. A contact area between the upper pad layer 40 and the connecting terminal 50 is reduced when the area of the pad electrode 12 is reduced. And the adherence intensity between the upper pad layer 40 and the connecting terminal 50 is reduced. The adherence intensity between the upper pad layer 40 and the connecting terminal 50 is further reduced when the void 52 is formed as shown in FIG. 2B. It is thus necessary to enlarge the upper region of the pad electrode.